1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as an electrically erasable and programmable ROM (EEPROM).
2. Description of the Related Art
As one of nonvolatile semiconductor memory devices, a NAND-cell type EEPROM capable of high integration is known. In this NAND-cell type EEPROM, a predetermined number of memory cells are connected in series with adjacent memory cells by sharing their sources and drains, and each group of in series-connected memory cells is connected to a bit line as one unit (NAND cell section). A general memory cell has a FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked. Memory cell arrays are integrated and formed in a P-type substrate or a P-type well region formed on an N-type substrate. The drain side of the NAND cell section is connected to the bit line through a first selection gate, and the source side is connected to a common source line through a second selection gate. The control gates of the memory cells are continuously arranged in a row direction to serve as word lines.
The operation of this NAND-cell type EEPROM is as follows.
Data programming is started from a memory cell at the furthest position viewing from the bit line. A high voltage Vpp (=about 20 V) is applied to the control gate of a selected memory cell, an intermediate voltage Vm (=about 10 V) is applied to the selection gate and the control gate of memory cells closer to the bit line than the selected memory cell, and 0 V or an intermediate voltage Vmb (=about 8 V) is applied to the bit line in accordance with data to be programmed.
When 0 V is applied to the bit line, the potential of the bit line is transferred to the drain of the selected memory cell, and electrons are injected into a floating gate to shift the threshold voltage of the selected memory cell in the positive direction. This state is defined as, e.g., "0".
When the intermediate voltage Vmb is applied to the bit line, no effective electron injection occurs. Therefore, the threshold voltage does not change and remains negative. This state is defined as "1" or the erased state.
Data are simultaneously programmed in memory cells sharing a control gate. A programming voltage Vpp is gradually increased to increase the programming speed while assuring the reliability of the memory cells. This is because abrupt application of a high voltage may destruct the tunnel portion of the memory cell.
Data are simultaneously erased from all memory cells in a NAND cell section. That is, all control gates are set to 0 V, and the P-type substrate or P-type well region is set to 20 V. At this time, a selection gate, a bit line, and a source line are also set to 20 V. With this operation, electrons of the floating gates in all the memory cells are discharged to the P-type substrate or P-type well region to shift the threshold voltages in the negative direction.
Data reading is performed by detecting whether a current flows in a selected memory cell while the control gate of the selected memory cell is set to 0 V, and the control gates and selection gates of remaining memory cells are set to a power supply voltage Vcc (e.g., 5 V).
Due to limitations in reading, a threshold voltage after "0" programming must be controlled to fall within the range of 0 V to the power supply voltage Vcc. For this reason, programming verification is performed to detect the memory cells in which "0" programming is insufficient and to set the reprogramming data such that the data is reprogrammed in the insufficient "0" programming memory cells (bit-by-bit verification). An insufficient "0" programming memory cell is detected by reading out (verify-read) the data at a selected control gate voltage of, e.g., 0.5 V (verification voltage). That is, if the threshold voltage of a memory cell is not 0.5 V (0 V+margin) or more, a current flows through a selected memory cell, and an insufficient "0" programming state is detected.
By performing data programming by repeating programming and programming verification, the programming time is optimized for each memory cell to properly control the threshold voltage after "0" programming to fall within the range of 0 V to Vcc. Since the programming voltage is increased in every programming step, programming is performed at high speed while assuring reliability.
In a NAND-cell type EEPROM of this type, the following problems are posed.
More specifically, the initial value of the programming voltage Vpp in programming must be set to be sufficiently low for a fast programmable memory cell while the final voltage must be set to be sufficiently high for a slow programmable memory cell. For this reason, when the increase rate of the programming voltage per unit of time is made constant, programming takes more time with a larger variation in the programming characteristics.
As this variation in programming characteristics becomes larger, programming and programming verification must be inevitably repeated a larger number of times, thereby prolonging the programming time.
Note that this problem is not limited to the NAND-cell type EEPROM and may be posed in another nonvolatile semiconductor memory device for performing programming/erasing data in/from a memory cell, e.g., a NOR cell type EEPROM.
As described above, in the conventional semiconductor memory device, if the variation in the programming characteristics of the memory cells is increased, the difference between the initial voltage and the final voltage of the programming voltage is increased, or the number of times of programming and programming verification is increased, thereby prolonging the programming time.